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From 2D to Monolithic 3D:
Design Possibilities,
Expectations and Challenges
O. Billoint1, H. Sarhan1, I. Rayane2, M. Vinet1,
P. Batude1, C. Fenouillet-Beranger1, O. Rozeau1,
G. Cibrario1, F. Deprat1, O. Turkyilmaz1,
S. Thuries1, F. Clermidy1
1Univ.
www.cea.fr
&
Grenoble Alpes, F-38000 Grenoble, France
CEA, LETI, MINATEC Campus, F-38054 Grenoble, France
2Mentor Graphics, 110 rue Blaise Pascal, 38330 Montbonnot-Saint-Martin, France
Outline
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• Why 3D, Why Now?
• What is Behind 3D-VLSI (Monolithic 3D)?
• Design Possibilities
• Expectations and Challenges
• Conclusion
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
|2
Context
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Delay of a single wire of the same circuit (s)
(extracted from internal DRMs)
5.00E-13
4.00E-13
3.00E-13
2.00E-13
1.00E-13
0.00E+00
Back End
performances
are decreasing
28nm
14nm
10nm
Process Node
TSV [1]
Size : 10x10um2
Pitch : 30um
7nm
Energy Efficiency
6.00E-13
3D Interconnect Technology
Cu-Cu [1]
Size : 1,7x1,7um2
Pitch : 2,4um
3D Physical implementation
Number of Design Rules
might
be an alternative
(Extracted from
PDKs)
20000
15000
10000
5000
Scaling is about
to be more and
more complex
3D-VLSI (28nm) [2]
Size : 0,05x0,05um2
Pitch : 0,11um
0
0,35um
65nm
28nm
14nm
Process Node
[1] Patti B., Tezzaron, inc. « Implementing 2.5D and 3D Devices »
AIDA workshop 2013
[2] Taken from internal Design Rules Manual
&
130nm
Olivier BILLOINT / CEA, LETI, Minatec Campus
HD-TSV [1]
Size : 0,85x0,85um2
Pitch : 1,75um
© CEA. All rights reserved
DACLE Division| March 2015
|3
Going 3D
for What?
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Reduce Footprint
Reduce
Wirelength
Reduce
Power
Reduce
Clock Period
Increase Yield?
Two half-size circuits better
than a full size one?
&
True if :
Vertical connections have ~100% yield
Circuits are not fabricated sequentially
Are we able to test half of a design
during process?!
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
|4
Interconnect
Flavors
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LDPC IP
28nm FDSOI
Reduce Footprint
Minimize
Reduce
3D interconnects
Wirelength
50% footprint
reduction
Inter-Tier vias:
5439
Area Overhead (% of 3D Footprint)
Reduce
Reduce
due to 3D Interconnect
for a LDPC IP
Power
100000.00
10000.00
1000.00
100.00
Clock Period
Back to 2D footprint
but with a 3D design!
Increase Yield?
10.00
1.00
Two
0.10 half-size circuits better
HD-TSV
thanTSVa full size
one? Cu-Cu
Monolithic 3D
[1] Patti B., Tezzaron, inc. « Implementing 2.5D and 3D Devices »
AIDA workshop 2013
[2] Taken from internal Design Rules Manual
Olivier BILLOINT / CEA, LETI, Minatec Campus
&
Technology
Size
Pitch
TSV (1)
10µm
30µm
HD-TSV (1)
0,85µm
1,75µm
Cu-Cu (1)
1,70µm
2,4µm
3D-VLSI 28nm (2) 50nm
© CEA. All rights reserved
110nm
DACLE Division| March 2015
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A 3D
Solution
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Research
15% Power savings
15% Performances gain
50% Footprint reduction
Commercial
[2] 2014
TSV
[1] 2004
Cu-Cu
?
201x
3D-VLSI
[1] Black, B. ; Nelson, D.W. ; Webb, C. ; Samra, N., « 3D processing technology and its impact on iA32 microprocessors »
Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004.
[2] « Samsung Starts Mass Producing Industry’s First 3D TSV Technology Based DDR4 Modules for Enterprise Servers »
Seoul, Korea on Aug. 28. 2014
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
|6
Outline
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• Why 3D, Why Now?
• What is Behind 3D-VLSI (Monolithic 3D)?
• Design Possibilities
• Expectations and Challenges
• Conclusion
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
|7
CMOS
Sequential
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CoolCubeTM process
developed at LETI
Copper Back-End
Inter-Tier vias
28nm node
Size: 50x50nm2
Pitch: 110nm
Like a contact
Specific «Cold»
CMOS Process
CoolCubeTM
Tungsten Back-End
Regular «Hot»
CMOS Process
Batude P. et al, « Demonstration of low temperature 3D sequential FDSOI integration down to 50nm gate length »
In Proceedings of IEEE Symposium on VLSI Technology, 2011
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
|8
TM Flavors
CoolCube
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Transistor Level
Gate (Standard Cell) Level
OneMainstream
MOS type onright
each now
tier
Not
CMOS on each tier
Process
Boosters3D
Friendly
- Lot
of intra-cell
vias
(SiGe / III-V / …)
- Lower standard cell density
Different Node / Process
Stacking
- Heterogeneous
Compatible withoriented
2D P&R
Not Compatible with 2D
P&R
Requires Standard Cells
redesign
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
No Standard Cells redesign
© CEA. All rights reserved
DACLE Division| March 2015
|9
TM Process Opportunities
CoolCube
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Homogeneous / Heterogeneous Integration
&
Soi
-------------Soi
Logic
-------------Memory
Soi
-------------Cmos
Sensor
-------------Logic
Soi
-------------Finfet
Analog
-------------Logic
Olivier BILLOINT / CEA, LETI, Minatec Campus
Sensor
-------------Analog
-------------Logic
-------------Memory
© CEA. All rights reserved
DACLE Division| March 2015
| 10
Outline
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du titre
• Why 3D, Why Now?
• What is Behind 3D-VLSI (Monolithic 3D)?
• Design Possibilities
• Expectations and Challenges
• Conclusion
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
| 11
DesignlePossibilities
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Homogeneous / Heterogeneous Integration
Soi
Logic
--------------------------Predictive
Design
Kit
Soi
Memory
(Full Custom Analog dedicated)
Soi
Sensor
--------------------------Basic Models, Parasitic
Cmos
Logic
Extraction, Layout
Soi
Analog
--------------------------1st
order
study
:
Ring
Finfet
Logic
Oscillators, small blocks
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
2D Design Platform
(For Digital
Design)
Sensor
-------------Analog
Plenty of 2D-------------files for 2D tools!
Logic
-------------Memory
Detailed Studies
(Performances, Power, Area…)
© CEA. All rights reserved
DACLE Division| March 2015
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3D-VLSI
Using Predictive
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titre
3D 14nm FDSOI Predictive DK
Application to FPGAs
Turkyilmaz, O. et al « 3D FPGA using high-density interconnect Monolithic Integration »
in Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
LB: Logic Block
SB: Switch Box
CB: Connection Box
CRAM : configuration RAM
© CEA. All rights reserved
DACLE Division| March 2015
| 13
3D-VLSI
2D Design
Platform
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Deflate / Inflate Standard
Cells to emulate 3D
placement
Splitting / Folding
Methodology to emulate 3D
placement
Single tier routing at a time
Tier to Tier routing in one
single run
Extraction of timing
informations tier by tier
Timing Analysis outside of
P&R tool
[1]
Timing-Driven routing
Single Tool Methodology
[2]
Useful methodologies to get some trends and concepts but then…
[1Shreepad P. et al, « Design and CAD Methodologies for Low Power Gate-level Monolithic 3D ICs »
In proceedings of ISLPED’14, August 11–13, 2014, La Jolla, CA, USA
[2] Billoint O. et al, « A Comprehensive Study of Monolithic 3D Cell on Cell Design Using Commercial 2D Tool »
In Proceedings of DATE’15, Grenoble, France
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
| 14
Outline
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du titre
• Why 3D, Why Now?
• What is Behind 3D-VLSI (Monolithic 3D)?
• Design Possibilities
• Expectations and Challenges
• Conclusion
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
| 15
Cliquez pour modifier Expectations
le style du titre
Market Expectations [1]
- 1 process node advantage
- PPA Gains
- 30% Power savings
- 40% Performances gain
- 52% Footprint reduction
[1] Dr. Karim Arabi, Qualcomm, Inc. “Keynote: Mobile Computing Opportunities, Challenges and Technology Drivers”,
51st Design Automation Conference (DAC), 2014.
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
| 16
Cliquez pour modifier leChallenges
style du titre
Which cell on which tier?
Design for Test (How do you test ½ chip?)
Process corners
Thermal behavior and workaround
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
| 17
3D
Benefits
Compared
to Scaling
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Start
A
Z
A
Z
A
Z
A
Z
A
Z
B
Distribute
cells on tiers
How do we
optimize?
Scaling benefits
were
(digital) design
independent
&
Cut the long
wire(s)!
Is there a possible better
ring oscillator in 3D?
3D Interconnect cost has to
be evaluated compared to
Wire cost
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
…
3D Stacking
benefits may be
architecture
dependent
DACLE Division| March 2015
| 18
Tier topour
Tier modifier
Interconnections
Cliquez
le style du (1)
titre
What’s the cheapest solution for point
to point connection, wire or via stack?
Trade
Wirelength
for
vertical
connection
Horizontal versus Vertical Routing @ 28nm
70
Resistivity (Ohm)
60
50
40
Vertical Routing (vias)
30
Horizontal Routing (Wires)
20
10
0
0
2
4
Distance (µm)
6
8
Above 2,5µm length, is it REALLY worth trading wires for vias?
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
| 19
Tier topour
Tier modifier
Interconnections
Cliquez
le style du (2)
titre
Tungsten
resistivity =
6x Copper
resistivity
Horizontal versus Vertical Routing @ 28nm
160
70
Adding 2µm of
Tungsten routing
140
60
120
50
100
40
80
30
60
20
40
(Ohm)
Resistivity
Resistivity (Ohm)
Trade
Wirelength
for
vertical
connection
What’s the cheapest solution for point
to point connection, wire or via stack?
Adding 1µm of
Tungsten routing
Vertical
VerticalRouting
Routing(vias)
(vias)
Horizontal
HorizontalRouting
Routing(Wires)
(Wires)
10
20
0
0
2 2
4
4
6
Distance
Distance (µm)
(µm)
6 8
8
10
Tungsten Back-End for bottom tier solves contamination issues (process)
Above 2,5µm length, is it REALLY worth trading wires for vias?
but creates constraints on tier to tier optimization
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
| 20
3D-VLSIpour
Concept
and
Ratio
Cliquez
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le Area
style du
titre
2D
hMetis [1]
PAP (40-60) [2]
Trade
Wirelength
for
vertical
connection
Tungsten
How
many
resistivity
long wires=
6x
to Copper
cut do
resistivity
we have?
Reconfigurable FFT
Aiming at 50/50 Area Ratio may not always be the
best solution for optimal PPA!
[1] Karypis, G., Aggarwal, R., Kumar, V., and Shekhar, S. “Multilevel hypergraph partitioning: applications in VLSI domain”,
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 1999, 7(1), 69-79.
[2] Physical Aware Partitioning developed at LETI
© CEA. All rights reserved
DACLE Division| March 2015 | 21
Olivier BILLOINT / CEA, LETI, Minatec Campus
&
Inter-Tier
Power le
Distribution
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Intra-Core power supply connections
are mandatory to limit IR Drop
Connecting to top tier Power
Distribution is the cheapest solution
Y-direction routing obstructions
Wire Length and Power Consumption
will be affected
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
| 22
Outline
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du titre
• Why 3D, Why Now?
• What is Behind 3D-VLSI (Monolithic 3D)?
• Design Possibilities
• Expectations and Challenges
• Conclusion
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
| 23
Cliquez pour modifier leConclusion
style du titre
ENABLING 3D-VLSI
I/Os and
ESDs
Process is on
the way!
50% Area
reduction
…etc
Tier-Specific
Area RatioProcess Corner
Specification
Tier-to-Tier Cell
Placement
Optimization
&
3D
Interconnects
are critical
Full 3D Routing
Thermal
in one
run with
Behavior
Timing
Closure
Power
Optimization
Inter-Tier Power
Supply
Distribution
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
| 24
Cliquez pour modifier leConclusion
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• Scaling was design independent
• 3D stacking might be different
• Wirelength reduction is a good goal to pursue as
Back End performances have started decreasing
• Preliminary studies using commercial 2D tools
(trustable) for what they’re not supposed to do
• Showing the real potential of 3D-VLSI will require to
tape-out, measurements, comparisons…
• And don’t forget that… 2 tiers is only the very
beginning!
&
Olivier BILLOINT / CEA, LETI, Minatec Campus
© CEA. All rights reserved
DACLE Division| March 2015
| 25
Centre de Grenoble
17 rue des Martyrs
38054 Grenoble Cedex
Centre de Saclay
Nano-Innov PC 172
91191 Gif sur Yvette Cedex
O. Billoint1, H. Sarhan1, I. Rayane2, M. Vinet1, P. Batude1,
C. Fenouillet-Beranger1, O. Rozeau1, G. Cibrario1, F. Deprat1,
O. Turkyilmaz1, S. Thuries1, F. Clermidy1
1Univ.
Grenoble Alpes, F-38000 Grenoble, France
CEA, LETI, MINATEC Campus, F-38054 Grenoble, France
2Mentor Graphics, 110 rue Blaise Pascal, 38330 Montbonnot-Saint-Martin, France
olivier.billoint@cea.fr
Thank You
olivier.billoint@cea.fr
Centre de Grenoble
17 rue des Martyrs
38054 Grenoble Cedex
Centre de Saclay
Nano-Innov PC 172
91191 Gif sur Yvette Cedex
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